MAX5938LEEE+【PDF 12/26 页】IC HOT-SWAP CTRLR -48V 16-QSOP

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Disabling Circuit-Breaker and

Short-Circuit Functions

In the MAX5938, the circuit-breaker and short-circuit

functions can be disabled, if desired, although this is

not recommended. (See Warning note in the PGOOD

Open-Drain Output section). This can be accomplished

by leaving CB_ADJ open. In this case, PGOOD asserts

1.26ms after GATE has ramped to 90% of full enhance-

ment, after which V

OUT

is ignored, resulting in the cir-

cuit-breaker and short-circuit faults being ignored.

PGOOD Open-Drain Output

The power-good output, PGOOD, is open drain and is

referenced to V

OUT

. It asserts and latches if V

OUT

ramps below 74% of V

, and with the built-in delay,

this occurs 1.26ms after the external MOSFET becomes

fully enhanced. PGOOD deasserts any time the part

enters fault management. PGOOD has a delayed

response to ON and OFF. The GATE will go to V

when OFF is brought below 1.25V (no time depen-

dence) while ON is brought below 1.125V for 1.5ms.

This turns off the power MOSFET and allows V

OUT

rise depending on the RC time constant of the load.

PGOOD, in this situation, deasserts when V

OUT

rises

above V

for more than 1.4ms or above V

whichever occurs first (see Figure 9b).

Since PGOOD is open drain, it requires an external

pullup resistor to GND. Due to this external pullup,

PGOOD does not follow positive V

steps as well as if

it were driven by an active pullup. As a result, when

PGOOD is asserted high, an apparent negative glitch

appears at PGOOD during a positive V

step. This

negative glitch is a result of the RC time constant of the

external resistor and the PGOOD pin capacitance lag-

ging the V

step. It is not due to switching of the inter-

nal logic. To minimize this negative transient, it may be

necessary to increase the pullup current and/or to add

a small amount of capacitance from PGOOD to GND to

compensate for the pin capacitance.

The PGOOD output logic polarity is selected using

POL_SEL input. For an active-high output, connect

POL_SEL to V

. Leave POL_SEL open for an active-

low output.

WARNING: When disabling the circuit-breaker and

short-circuit functions (CB_ADJ open), PGOOD asserts

1.26ms after the power MOSFET is fully enhanced inde-

pendent of V

OUT

. Once the MOSFET is fully enhanced

and ON and OFF are pulled below their respective

thresholds, the GATE will be pulled to V

to turn off the

power MOSFET and disconnect the load. When the cir-

cuit-breaker and short-circuit functions are disabled

and ON and OFF are cycled low, PGOOD is deassert-

ed. In summary, when CB_ADJ is open (once the MOS-

FET is fully enhanced), the MAX5938 ignores V

OUT

and

deasserts PGOOD only for an overvoltage fault, when

ON and OFF are cycled low or when the power to the

MAX5938 is fully recycled.

Figure 9. ON and OFF Timing Diagram

(a)

220ms

LOAD-PROBE

DETECTION TEST

BEGINS

ON_REF,R

OFF

OFF_REF

1.3ms

ON_REF,F

OFF_REF

OFF

GATE

OUT

PGOOD

(b)

-48V Hot-Swap Controller with V

Step Immunity,

No R

SENSE

, and Overvoltage Protection

12 ______________________________________________________________________________________

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